How to determine the maximum and minimum of input delay?

Hi,

I already mentioned that register tSU/tH is inherent to device(also called micro tSU/tH. When viewed from device pins, the timing window shifts as explained in the equations. It is these delays that are the backbone of getting timing right. i.e. the fpga has configurable tSU/tH unlike ASICs which usually have fixed tSU/tH in their spec. In all cases we refer to pins because that is what is relevant to the designer.

Regarding output delays, We are talking about input delays. That is a different story and depends on tSU/tH of external device.