How to determine the maximum and minimum of input delay?

Hi kaz!

Thank you so much for your suggestion about the input delay.but there is something that I still can't understand.

You show me the "tsu(at pin) = data delay - clk delay + tsu(at register) th(at pin) = clk delay - data delay + th(at register)"

but I think the tsu and th are determined by the devices rather than the data delay ,tsu and clk delay.

The output delay is also confused to me,according to my projections I think the Output Minimum Delay and Output maximum Delay should be "output minimum delay = th - <max data delay> + <min clock delay>

output maximum delay=t(period)+<max clock delay>-<min data delay>-tsu",but the truth is not so.Some data shows that "output delay max= (tdata_pcb(max) + tcl) - (tclk2(min) - tclk1ext(max) ) + tsu output delay min= (tdata_pcb(min) + tcl) - (tclk2(max) – tclk1ext(min) ) - th".it's indigestible!

thank you very much!