how to decide read time from SDRAM via SDRAM controller

Thanks for your reply. The whole devices are used for real image processing. The clock i used for FPGA and SDRAM are the same 50MHz. And SDRAM controller is already included in the sysem. Just as you said we set up the parameter as follow:

CAS latency cycles 2;

Initilization refresh cycles 2;

Issue one refreshcommand cycles 7.5 us;

Delay after powerup, before initilization 100us;

Duration of refresh command(t_rfc) 66ns;

Duration of the precharge command(t_rp) 20ns;

ACTIVE to READ and WRITE delay (t_rcd) 20ns;

Access time(t_ac) 5.5ns

Write recovery time (t_wr, No auto precharge) 15ns;

I have to write a User Logic which has the function to write data to SDRAM and read data from SDRAM. For simplicity I just write a 8 bit data to SDRAM and the Data Width of memory profile is 64 bits. I need to write a process to determine how many clocks it will take after I sent the Address to SDRAM controller until the READDATA arrives at User_Logic. By the I am new in VHDL programming.