how to decide read time from SDRAM via SDRAM controller

It depends on used memory chips. In SDRAM you can set a parameter called latency and it will determine number of clock cycles between read request and data appearance on the memory bus. Usually this takes from two to four clock cycles. If you want fast memory access you can just rise memory clock frequency. Of course, I assume that memory controller will be synthesised in your FPGA :] Another soluction is to use SRAM memory. It is faster than SDRAM, but has less capacity.

If you want to know how to implement SDRAM controller in VHDL I will present here one of possible soluctions ;)

Let us assume that your FPGA has a 50 MHz clock and you want to strobe SDRAM with same 50 MHz clock. So:

SDRAM_ctrl : process (clk,rst) is

begin

if rst='1' then --assumed reset signal active high

counter <= "0000000000"; --counter is 10 bit std_logic_vector

elsif rising_edge(clk) then --you can use falling_edge(clk) if it's more convenient

if counter = 10 then --this is just an example. The point is that counter

SDRAM_cs <= '0'; --precisely determines moments when RAM control

end if; --or data signals should change

if counter = 11 then --for precise timing waveforms refer to your SDRAM

SDRAM_ras <= '0'; --datasheet

end if;

end if;

end process SDRAM_ctrl;

Hope, I helped you ;)