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Altera_Forum
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8 years ago

how to create matrix in VHDL

Hi guys! I am trying to create a matrix or an array. 4 columns and 2 rows. Is my code correct? type row_t is array(0 to 3) of std_logic_vector(7 downto 0); type matrix_t is array(0 to 1, 0 ...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Yes, it is a matrix

2d matrices cannot be slices, so you need to assign individual elements.

You could build it with 1d arrays, which can be sliced to apply an entire row.