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Honored Contributor
Honored ContributorHow to create delay cell
I am trying to create a frequency doubler using an Xor and a DFF. However it requires a delay cell to create finite pulse width for the signal. I am using functional sim. Does the cell exist in the l...
Altera_ForumHonored Contributor
Honored Contributor.. the design software allow use PLL block. How to questions described in "clocking and PLL User Guide".
the VHDL 'after' construct only for sim. you should take lessons for digital schematic to build your own PLL )) just delay the input clock for 1/4 of period
