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Altera_Forum's avatar
Altera_Forum
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11 years ago

how to creat noise signal in vhl

i have problems: How to creat noise gaussian or normal noise in vhdl ??? and how to simulate sine wave and sin wave+ noise in modelsim altera
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

VHDL does have a "uniform" function in the math_real package than can generate random numbers between 0.0 and 1.0, that you can use to inject randomness into your design.

Also, have a look at this http://osvvm.org/

It is a package of functions for constrained random generation with various distrubutions (including gaussian)