Altera_ForumHonored Contributor11 years agohow to creat noise signal in vhl i have problems: How to creat noise gaussian or normal noise in vhdl ??? and how to simulate sine wave and sin wave+ noise in modelsim altera
Altera_ForumHonored Contributor11 years ago --- Quote Start --- Are you talking about creating noise only for simulation, or from an FPGA? --- Quote End --- just for simulation,thanks
Recent DiscussionsUSB-BlasterII mounts as "USB-Blaster variant"Quartus Dark Theme on Linux - SolutionError(23098) when using IPM_IOPLL on Agliex 7Quartus 13.1 LicenseHighlight similar instances of a selected word fails when scrollingSolved