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Altera_Forum's avatar
Altera_Forum
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15 years ago

How to control fan out of an asynchrounous signal

Hi,

We had a design let say would be replicated more than 8000 times or would generate 8000 of fan-out for the reset signal.

Module:process(reset,clock)

Begin

If (reset=’1’) then

Some operation

Else if rising_edge(clock) then

Some operation

End if

End process Module

Had tried

force the signal to non global resource, -> causing that to failed for the recovery time.

Max_fanout setting used to control this net and duplicate the flip-flop. -> failed

This node feeds to an asynchronous control port -> attached is the picture.

For this case, can we still set false path in between the register? Or need rerouting? Or there is any assignment setting that need to set? To control the fan-out of an asynchronous signal in Quartus.

Thanks in advance for the help

Best regards

kenny

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You didn't report, if you observed any problems, if you just let Quartus do it's work? I assume none.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Dear FVM,

    Thanks for your response,

    the Quartus shows “Warning: Ignored Maximum Fan-Out assignment”

    We try use MAX_FANOUT setting to control the net and to duplicate the flip-flop driving this net. Unfortunately, this cannot be used because the node feeds to an asynchronous Control ports. You may refer to the picture above.

    http://www.altera.com/literature/hb/qts/qts_qii5v1_03.pdf (http://www.altera.com/literature/hb/qts/qts_qii5v1_03.pdf) -> page 9-47

    So how do we control the fan-out for an asynchronous signal in Quartus?

    Thanks in advance,

    Best regards

    Kenny
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Had tried also

    PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING & ASYNC_PIPELINE_REG_REACH setting to duplicate the source register but failed.

    thanks

    regards

    kenny
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi,

    Had tried send a mail, but i guess it failed to send. It initially failed for the recovery timing in Time Quest.

    thanks

    regards

    kenny
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Please excuse my penetrant asking, it wasn't actually clear to me. I think, it's not mainly a fanout problem rather than of achieving the correct timing for the reset signal along the clock path at a rather high clock frequency. Avoiding asynchronous controls for fast registers simplifies timing closure a lot. Do you really need an asynchronous reset?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    To understand the Quartus behaviour with signal fanout, I set up a simple circuit with 8000 registers (simply connected as a shift register chain) and a reset synchronizer driving the asynchronous reset of each register.

    With Cyclone III, Quartus used a global clock resource to connect the reset signal and had no problem to achieve 250 MHz clock rate.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Dear Fvm,

    Thanks for your input, I am using Stratix II EP3SE110F78014 and the fan out is about 60000. The result show slack ~-0.7 and End Point TNS ~-4000.

    By improving the TNS, I had tried to set the following

    1) set the global signal to off in the assignment editor.

    2) Increase the Effort level to Extra in the setting

    3) Perform automatic asynchronous signal pipelining in the setting

    And the result shows TNS ~-3000 in improvement. Is there anything that I can do to improve the TNS? I am following the guideline from the attached notes.

    Thank for your patient and help.

    Best regards

    Kenny
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    After long reseach, Quartus does not encourage do reduce the max fan out. However, we can set some setting in the QSF file to control it:

    set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED "ALWAYS ALLOW" -to

    set_instance_assignment -name MAX_FANOUT 500 -to

    set_instance_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS OFF to

    set_instance_assignment -name MAX_FANOUT 500 -to

    set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED "ALWAYS ALLOW" -to

    set_instance_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS OFF -to

    set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED "ALWAYS ALLOW" -to

    set_instance_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS OFF -to

    set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON

    set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON

    set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON

    set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON

    set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON

    set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON

    set_instance_assignment -name MAX_FANOUT 500 -to set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED "ALWAYS ALLOW" -to

    set_instance_assignment -name MAX_FANOUT 500 -to set_instance_assignment -name ADV_NETLIST_OPT_ALLOWED "ALWAYS ALLOW" -to

    set_instance_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS ON -to