Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

How to control fan out of an asynchrounous signal

Hi, We had a design let say would be replicated more than 8000 times or would generate 8000 of fan-out for the reset signal. Module:process(reset,clock) Begin If (reset=’1’) then S...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

To understand the Quartus behaviour with signal fanout, I set up a simple circuit with 8000 registers (simply connected as a shift register chain) and a reset synchronizer driving the asynchronous reset of each register.

With Cyclone III, Quartus used a global clock resource to connect the reset signal and had no problem to achieve 250 MHz clock rate.