i need to use gated clock in my design, and like following: module prac ( a, b, rst_n, out ); input a; input b; input rst_n; output out; reg out; wire c; assign c = a && b; always @ (posedge c or negedge rst_n) begin if (!rst_n) out <= 1'b0; else if (c == 1) out <= ~out; end endmodule i know that using gated clock is not recommanded in sync design,but i need to do,and i don't know how to constraint the gated clcok, somebody help me?

what are the properties of a and b? are they both masked clocks or one is clock and the other - masking signal? do you intend c to be edge aligned with a/b?

--- Quote Start --- what are the properties of a and b? are they both masked clocks or one is clock and the other - masking signal? do you intend c to be edge aligned with a/b? --- Quote End --- a and b are both not clock, they are the signals changed between 0 and 1, the relationship between a and b are uncertain&#12290; the FAQ of altera say i can use"generated clock"command to constraint the output of "and" gate,but i still didn't know how to do this.

If a and b are uncertain, which means the clock waveform at the output of c is uncertain, they TimeQuest (or Classic) won't be able to analyze this design. For TimeQuest to be effective, you need to properly define the clock waveform characteristics. Even if you define two clocks in input a and b, TimeQuest will simply analyze a as if b does not exist, and b as if a does not exist, but it won't analyze the generated clock in c. In other words, without the proper clock waveform in c, TimeQuest will not do a proper setup and hold analysis.

--- Quote Start --- If a and b are uncertain, which means the clock waveform at the output of c is uncertain, they TimeQuest (or Classic) won't be able to analyze this design. For TimeQuest to be effective, you need to properly define the clock waveform characteristics. Even if you define two clocks in input a and b, TimeQuest will simply analyze a as if b does not exist, and b as if a does not exist, but it won't analyze the generated clock in c. In other words, without the proper clock waveform in c, TimeQuest will not do a proper setup and hold analysis. --- Quote End --- thanks, my design can work well, even if i don't constraint the c, but just some warnings when compliered. maybe i will try this using DC, it supports gated clock constraint.

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Altera_Forum

Honored Contributor

17 years ago

how to constraint the gated clock in the Timequest？

i need to use gated clock in my design, and like following:

module prac (

rst_n,

out

);

input a;

input b;

input rst_n;

output out;

reg out;

wire c;

assign c = a && b;

always @ (posedge c or negedge rst_n)

begin

if (!rst_n)

out <= 1'b0;

else if (c == 1)

out <= ~out;

end

endmodule

i know that using gated clock is not recommanded in sync design,but i need to do,and i don't know how to constraint the gated clcok, somebody help me?

11 Replies

Altera_Forum
Honored Contributor
17 years ago
--- Quote Start ---
O.K. can you tell about the expected a and b timing? Of course, if minimum H and L pulse widths are guaranteed for (a && b), there's probably no problem
--- Quote End ---

when a && b == 1, it will keep at least two period---40ns, and a && b == 0,it will keep at least 10us.
and a,b maybe flip high at the same time, that is uncertain.

Forum Discussion

how to constraint the gated clock in the Timequest？

11 Replies

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