How to Constraint Source-Synchronous Double-Data Rate Interfaces

If using -reference_pin, there's only one clock you've defined, so it would list them as the same clock in the summary section. If using generated_clock, it should be a different latch clock. The important thing is item 1) above. The latching clock is the clock coming into the FPGA, through the FPGA, and out the clock port you've designated.

If you don't know what the frequency is, then a PLL won't work. (You could probably do something complicated. Note that PLL's work over a range, i.e. if a PLL is running at 100MHz, you could probably fluctuate it's input by at least 20MHz. So if you had some oversampling circuit that could determine roughly the PLL frequency... anyway, you get the idea, and that it would be a PITA)

Setup and hold should be equivalent in a source synchronous interface. Basically that means the receiving device went through the pains to make sure the clock and data are equivalent in that device. Many source-synchronous interfaces specifcy skew, i.e. the transmitter may have 500ps of skew between clock and data, and the receiver can accept up to 500ps of skew, or something like that. If the Tsu and Th of the receiving device are not equivalent, that may be their way of saying they've phase-shifted the clock for you, or something like that..

For your last paragraph, the clock and data delay are almost the same whether you use a PLL or not. Remember that the data output delay is:

clock input -> possibly through a PLL -> global clock tree -> Tco of DDR register in IO cell -> Output delay

The clock path should pretty much look identical(at some point the clock tree splits, one path to feed the data and one to feed the clock). But as you can see, adding a PLL or not affects both paths equally, so it doesn't hurt. If the PLL wasn't used to feed the data too, then it would be a problem.

My recommendation is to close timing on the 165MHz, and in theory you should meet timing on all the lower frequencies(assuming Tsu/Th are equivalanet requirements). When you go to slower rates you'll just barely make timing on setup and tons of hold margin, but as long as you meet timing it doesn't matter.