Honored Contributor
Honored Contributorthanks for the quick response!
i will check the report again tomorrow but if i'm not wrong i was returning same source and destination clocks. regarding mixed settings is that i first tried without the reference clock and i still got the same input and output clock in the report. probably this comes from the fact input and output clocks are just hardwired however i assume the report should take into account the delay from internal logic to the pin while it seems to me the report i always seems to consider output pin data clocked by the internal node (pin), not the external pin (port). as i mentioned i would love to use a PLL however reconfiguring it on the fly would require knowing the input frequency which is not possible as i don't have a fixed frequency clock to measure the input one. in addition to this i don't completely understand the reason for 90 degrees shift as this seems to reduce the actual timing window since hold time is usually much shorter than setup hence i guess that in a system where data changes some time after clock you get the best window since you have huge setup and small hold which usually is sufficient. using the PLL of course allows shifting the clock with a fixed relationship to the input one however data will still have delays that vary with PVT and i assume the variation would be proportional to the one the clock would have if it doesn't have a PLL in the path hence in source synchronous not using a PLL should somehow increase the timing window rather than reduce it... what am i missing? thanks!!!
