Honored Contributor
Honored Contributor1) Run report_timing with the -detail option set to full_path. Then look at the Data Required Path. It should start from the iDCLK and trace through the FPGA to oDCLK.
2) You're mixing constraints above. You're doing a generated_clock on the output port, yet the set_output_delay constraint doesn't use this clock, and instead uses DCLK and -reference_pin. Both should work, but I recommend not using -reference_pin, and instead having "set_output_delay -clock ODCLK..." 3) I assume this is double-data rate? The reason a PLL is generally used is because it doesn't vary over PVT. Let's look at 166MHz clock, or a 3ns data window. To center the clock on the data, the clock or data path must be delayed 90 degrees, or 1.5ns. Delays vary considerably over PVT. So in the slow model, it might have to add 2ns, which is 1ns in the fast model. Basically a whole 1ns of variance is wasted that cuts into your data window. If a PLL were used to shift the clock 1.5ns, it would be shifted 1.5ns at the slow and fast models. 4) You're running at a slow enough rate that you might be able to get away with it. Source-Synch interfaces run at 300MHz+ for DDR2/3 and at 1Gbps for LVDS. At those rates, that variances wouldn't be acceptable. (One soulution for you would be to use a PLL and reconfigure it for different frequencies. It's not simple to do, but not that difficult.)
