how to constrain timing between FPGAs?

This is why I mentioned that you need to end up with one SDC file for each FPGA that will formalize the allocation of a portion of the budget. You can use set_max/min_delay, but the proper way is to use set_input_delay and set_output_delay to represent the external view of the requirement.

Imagine you have a 10ns Period, you can have:

FPGA1:

set_input_delay -clock [get_clocks clk] [get_ports in] 6ns

FPGA2:

set_output_delay -clock [get_clocks clk] [get_ports out] 4ns

More examples:

See http://www.altera.com/literature/hb/qts/qts_qii53024.pdf (http://www.altera.com/literature/hb/qts/qts_qii53024.pdf) and/or http://www.alterawiki.com/wiki/timequest_user_guide (http://www.alterawiki.com/wiki/timequest_user_guide) and/or http://www.altera.com/literature/manual/mnl_timequest_cookbook.pdf (http://www.altera.com/literature/manual/mnl_timequest_cookbook.pdf)

Once you correctly constraint each FPGA (based on your budget), you should be ok, even after some modifications to either FPGA. Of course, if something changes dramatically, then you may need to adjust your budgeting, which is when you need to go back to the original method.