how to constrain timing between FPGAs?

Martin,

In short, there is no solution but to do budgeting. And unless you have a lot of experience with the given device, you will need to do some iterations to find the right balance between your source and destination FPGA.

Because you have a chicken and egg type situation, you will need to pick one of the two FPGAs and use it as a base line. You can then use report_datasheet to get the delays, and use them to determine the input/output delay constraints for the second FPGA. At a high level, the Tsu becomes the output_delay of the other FPGA, and the Tco becomes the input_delay. But after that, you should apply the input/output delay constraints to the first FPGA, so you can be sure you are meeting timing on any subsequent compile.

Of course, you can go the easy route, and simply give 50% of the budget to one FPGA and 50% to the other. But again, the critical part is to then create the proper SDC file to represent the constraint assumptions you are making (for both FPGAs), and then simply let TimeQuest give you a slack report. If the slack is positive, you are done.

Don’t forget to model the board delay into your calculations.

Hope this helps.