how to constrain this?

I ended up doing this and it worked fine except it won't check the output of the slow module when data from it is clocked into the faster portion but not a critical issue for me as I don't try to do any work on that stage. Still if there's a better method I'd be interested. I wasn't sure if I'd need to do a false path from the slowclk to everything but the slowmodule and maybe it might speed up timing analysis but didn't cause any strange timing errors by not doing it.

# define 2 versions of the same clk

create_clock -name {fastclk} -period 6.8 [get_ports {clk}]

create_clock -name {slowclk} -period 12.5 [get_ports {clk}]

# avoid incorrect timing checks from output of slow module back into faster running stages

set_clock_groups -asynchronous -group [get_clocks { fastclk }] -group [get_clocks {slowclk}]

# mark false paths on fast clk to the slower module

set_false_path -from {fastclk} -to {slowmodule|*}

# maybe I should do false path from slowclk to everything but the slowmodule?