Honored Contributor
Honored ContributorHard to say exactly without knowing how it's constrained. Assuming you have a 25MHz and 150MHz constraint on the input, so all the logic is constrained at both frequencies, then for the relevant blocks you probably want to lower the requirement with something like:
set_max_delay -from {slow_blk|*} -to {slow_blk|*} 40.0 If you have any logic that uses falling edge clock, then it's probably safer to cover that with: set_max_delay -rise_from {slow_blk|*} -rise_to {slow_blk|*} 40.0 set_max_delay -fall_from {slow_blk|*} -fall_to {slow_blk|*} 40.0 set_max_delay -rise_from {slow_blk|*} -fall_to {slow_blk|*} 20.0 set_max_delay -fall_from {slow_blk|*} -rise_to {slow_blk|*} 20.0 (The hold time could also be loosened with a set_min_delay, but I'm assuming the hold requirement of 0ns is correct). This also assumes you don't have any multicycle paths in these blocks.
