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frwo's avatar
frwo
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6 years ago

How to constrain the phase shift to synchronized/generated non-overlapping clocks in SDC?

Hello! I'm currently struggling to properly set up my SDC file for a non-overlapping clock generator: What I have is a 100Mhz clock for the FPGA (used for the synchronizer) and an external 0,987Mhz...
frwo's avatar
frwo
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6 years ago

Hello sstrell,

thanks for your answer. Why isn't it a system-synchronous design? I have an external clock (phi0; ~1MHz) which is used as a basis for some of the external signals and at the same time

also my generated (but still synchronous) clocks that are also used as launch and latch clocks for some signals!?

And did I get that right:

I need to constrain the INTERNAL output of the clock generation logic pins via create_generated_clock (more or less as posted) BUT additionally also

the output ports again via set_generated_clock with multiply_by 1?

In other words: 2x create_generated_clock commands per generated clock? (1x Internal pin + 1x external port)?

BTW: I constrained the output port as data port because the whole design is a multi-mode device:

// Assign outputs
assign devPort_o[0] = (cfg == 4'h0) ? clk_phi1 : data_enable;
assign devPort_o[1] = (cfg == 4'h0) ? clk_phi2 : clk_phi1;

As you can see I'm muxing signals and clocks to a signal output port! (BTW: It's a pity that TimeQuest doesn't support set_case_analysis which seems to be made for this as I'll have 6 different operating

configuration 4'h0 <= cfg <= 4'h5).

How to do that one correctly?

Thanks,

Frank

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    6 years ago

    "I need to constrain the INTERNAL output of the clock generation logic pins via create_generated_clock (more or less as posted) BUT additionally also

    the output ports again via set_generated_clock with multiply_by 1?"

    Correct.

    "In other words: 2x create_generated_clock commands per generated clock? (1x Internal pin + 1x external port)?"

    Correct.

    For devPort_o, that is tricky. You can't false path devPort_o[0] because you do have it as a data output in one case, so you should be OK with clk_phi1 as a generated clock on that output port and data_enable constrained with set_output_delay to the same port. For devPort_o[1], you would have the 2 output clocks as generated clocks targeted to that output port (use -add for the second generated clock since it is targeted to the same port) and use set_clock_groups with the -exclusive option. You should false path that output since there is no data output on it.

    #iwork4intel