How to constrain the phase shift to synchronized/generated non-overlapping clocks in SDC?

You're essentially creating source synchronous-like interfaces here. A few things:

1) You don't need set_input_delay for clock inputs (clk_phi0_i). Once an input is defined as a clock, it's not a data path so this is not necessary.

2) Output clocks should not have set_output_delay constraints. They should have generated clock constraints where the source is some internal clock pin (like the output of a PLL or the output of your clock generation logic), the target is the output clock port (clk_phi1_o, clk_phi2_0), and the relationship to the source is a multiply_by 1. This makes the tool look at the output as a clock path instead of a data path. Once you've created the generated clock constraints, false path the clock output paths (ex.: set_false_path -to [get_ports clk_phi1_o]), so they are not analyzed as data paths. Data outputs that are clocked at a "downstream" device by these output clocks should have set_output_delay constraints and reference the generated output clock.

3) For tst_signal, you need to tell the tool to only analyze on the rising edge of clk_phi0_virt (launch edge) and the falling edge of clk_phi2 (latch edge). To do this, you need false path timing exceptions to indicate when the tool should not perform an analysis:

set_false_path -rise_to [get_clocks clk_phi2]

I'd recommend checking out the online training about constraining single data rate source synchronous interfaces, which is essentially what you're doing here:

https://www.intel.com/content/www/us/en/programmable/support/training/course/ocss1000.html

#iwork4intel