How to constrain the delays from ports to combinational block?

Hi, Thank you for the reply.

Here is my SDC file:

create_clock -name input_clock -period 20.000 [get_ports {CLOCK_50}]
create_clock -name rx_xor      -period 4.0    [get_pins {rx_gen_clock|combout}]
 
derive_pll_clocks
 
set_false_path -from [get_clocks {input_clock}] -to [get_clocks {u_tx_pll|tx_pll_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk u_tx_pll|tx_pll_inst|altera_pll_i|general[0].gpll~FRACTIONAL_PLL|vcoph[0]}]
 
set_false_path -from [get_registers *async_rx*] -to [get_registers *error_counter*]
set_net_delay -from [get_registers *async_rx*]  -to [get_registers *error_counter*] -max -get_value_from_clock_period dst_clock_period -value_multiplier 0.8
 
set_max_delay -from [get_ports {RX[0] RX[1]}] -to [get_pins {rx_gen_clock|combout}]  8
set_min_delay -from [get_ports {RX[0] RX[1]}] -to [get_pins {rx_gen_clock|combout}]  7.5

Report data path:

report_path -from [get_ports {RX[1] RX[0]}] -to [get_pins {rx_gen_clock|combout}] -npaths 100 -panel_name {Report Path} -multi_corner
 
Delay       From      To 
7.512	RX[0]	rx_gen_clock|combout
5.627	RX[1]	rx_gen_clock|combout

And the paths in chip planner:

That essentially what I want to do (I could make the tx_pll clock 200 Mhz by using ddo registers for the outputs)

Btw, I have synthesized it once and it kinda worked, so I could transmit data at 400 Mbps between two FPGAs (sending just an incrementing counter and checking on the other side that I got the right value),

but it's too unreliable especially if I slightly change the code then everything changes. Thanks