How to constrain my design

Hi Dave,

You are correct about your assumption. I actually tried your proposal, but like you said "I" have taken care of the clock crossing and TimeQuest will not tell me if I messed up somewhere and this got me thinking... I know that it takes the data ready signal around 12 ns to be synchronized to from clock A domain into clock E domain. Doesn't this mean that I have to tell TimeQuest that the data from clock A domain needs to be stable at clock E domain before 12 ns, which is the point where the data gets captured from clock A domain?

I'm thinking that I need to put the following commands in the SDC file:

- set_max_delay -from [get_clocks {clk_a}] -to [get_clocks {clk_b}] 11 ns

- set_max_delay -from [get_clocks {clk_b}] -to [get_clocks {clk_a}] 11 ns

Is this assumption correct?

Br,

David