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There is only a single 32 bit databus crossing the clock domains and with the databus is a write strobe, which has been synchronized to the new clock domain.
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So you have an interlocked handshake? Eg. something like:
1) Clock domain A writes the data to the data register, and asserts the "data is ready" signal.
2) A synchronizer synchronizes the "data is ready" from the clock A domain into the clock E domain.
3) Logic in the clock E domain enables a register to capture the data from the clock A domain.
If that logic is in place, then *you* have taken care of the clock synchronization issues, and so you need to communicate this to TimeQuest by telling it to ignore signals that cross the clock domains, eg.,
# Clock A and virtual clock for I/O constraints
create_clock -period 10MHz -name clk_a
create_clock -period 10MHz -name vclk_a
# Clock B and virtual clock for I/O constraints
create_clock -period 25MHz -name clk_b
create_clock -period 25MHz -name vclk_b
# Clock groupings
set_clock_groups -exclusive -group -group
The clock groupings separate the analysis of clock A and B, and tell TimeQuest that you've taken care of clock crossing.
Let me state that again just to emphasize it; that "YOU" have taken care of clock crossing. If you forget to include synchronizing logic, or you do it wrong, TimeQuest will not tell you :)
Cheers,
Dave
Honored Contributor
