How to constrain a source-synchronous desing?

When you say there is some setup slack, I assume you mean "negative slack", i.e. it's failing?

You have a 5ns setup relationship(10ns clk period with launch at 5ns and latch at 10ns), and an external delay of 2.0(I'm not sure how it went from 1.2 Tsu to 2.0, but that may be board delay, clock skew, margin, etc.). Anyway, that ends up with 3ns for the FPGA, which it should be able to meet pretty easily, since the clock and data delays shuld match.

Can you look at the data path going out(Data Arrival) and clock path going out(Data Required) and see if there is something physically different? The one thing I see commonly is that users use the dedicated PLL clock output, rather than just a regular I/O. That path doesn't use a global(would show up as type CLKCTRL in your data required path). Maybe post the timing report here.