How to constrain a source-synchronous desing?

My design outputs a 125Mhz Clk and 10-bit data to the downstream device.

The 125Mhz clock is inverted from a dedicated clock-pin.

The 10-bit data is launched at the rising edge of the original clock.

The downstream device requires a setup = 1.2ns and hold = 0.2ns.

My constrain command is as follows:

create_clock -period 8 -name clk [get_ports {clk_in}]

derive_pll_clocks

create_generated_clock -name clk_out -source [get_ports {clk}] -invert [get_ports {clk_out}]

set_output_delay -clock { clk_out } -max 2.0 [get_ports {da_t*}]

set_output_delay -clock { clk_out } -min -0.2 [get_ports {da_t*}]

The TQ report some SETUP SLACK.

If anybody can explain that for me?

Any and all help is very much appreciated

Harris