Honored Contributor
Honored ContributorIf edge aligned:
create_clock -period 16.0 -name ssync_clk [get_ports ssync_clk_in] derive_pll_clocks derive_clock_uncertainty create_clock -period 16.0 -name ssync_ext set_input_delay -clock ssync_ext -max 2.0 [get_ports {ssync_data[*]} set_input_delay -clock ssync_ext -min -2.0 [get_ports {ssync_data[*]} set_input_delay -clock ssync_ext -max 2.0 [get_ports {ssync_data[*]} -clock_fall -add_delay set_input_delay -clock ssync_ext -min -2.0 [get_ports {ssync_data[*]} -clock_fall -add_delay That assumes the PLL is shifting the clock 90 degrees to center it on the data. (It doesn't have to do that, but things get trickier). I put in delays of 2.0 and -2.0. Basically that says the upstream chip and board delays will skew the data by +/-2.0ns in relation to the clock. You need to change those to the correct value. # ################# If the upstream device sends its data center-aligned, then change the virtual clock to be: create_clock -period 16.0 -waveform {4.0 12.0} -name ssync_ext All that says is the clock is phase-shifted 90 degrees externally, so the clock is coming centered on the data eye. Your PLL shouldn't do a phase-shift now. (Oh, and when creating the PLL, make sure it is in source-synchronous compensation mode. At these speeds it probably doesn't matter, as you can make timing anyway, but it's good practice)
