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Artak's avatar
Artak
Icon for New Contributor rankNew Contributor
3 years ago
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How to connect 32bit master to 8GB ddr memory using Qsys interconnect.

I'm using a board with Agilex FPGA and 8 GB DDR4 memory. I'm trying to connect a 32bit AXI master (a soft cpu core) to DDR controller in Platform Designer. The Platform Designer interconnect autom...
  • Shawn_S_Intel's avatar
    Shawn_S_Intel
    3 years ago

    I recommend the Address Span Extender component. It allows you to set a window into a larger memory space. The example given in the documentation is your use case:

    For example, an HPS subsystem in an SoC device can address only 1 GB of an address span within the FPGA, using the HPS-to-FPGA bridge. The Address Span Extender enables the SoC device to address all the address space in the FPGA using multiple 1 GB windows.

Shawn_S_Intel's avatar
Shawn_S_Intel
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

I recommend the Address Span Extender component. It allows you to set a window into a larger memory space. The example given in the documentation is your use case:

For example, an HPS subsystem in an SoC device can address only 1 GB of an address span within the FPGA, using the HPS-to-FPGA bridge. The Address Span Extender enables the SoC device to address all the address space in the FPGA using multiple 1 GB windows.