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Artak's avatar
Artak
Icon for New Contributor rankNew Contributor
3 years ago
Solved

How to connect 32bit master to 8GB ddr memory using Qsys interconnect.

I'm using a board with Agilex FPGA and 8 GB DDR4 memory. I'm trying to connect a 32bit AXI master (a soft cpu core) to DDR controller in Platform Designer. The Platform Designer interconnect autom...
  • Shawn_S_Intel's avatar
    Shawn_S_Intel
    3 years ago

    I recommend the Address Span Extender component. It allows you to set a window into a larger memory space. The example given in the documentation is your use case:

    For example, an HPS subsystem in an SoC device can address only 1 GB of an address span within the FPGA, using the HPS-to-FPGA bridge. The Address Span Extender enables the SoC device to address all the address space in the FPGA using multiple 1 GB windows.

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi Artak,


Thank you for submitting your question in Intel Community.

I am Adzim from Penang Application Engineer will assist you in this thread.


The address map can be changed only for Base address. The End address is already determined with the address range.


"How to modify the address range in order to limit DDR access within 0x00000000 -0x80000000?"

The address range is determined by the Quartus based on the IP setting.

For EMIF IP, the DQ width is main factor to effect the address range.

If you can reduce the DQ width, then the address range will also decrease.


Regards,

Adzim