How to configure the PCIe Hard IP block on a Stratix V GX FPGA Development Kit using Quartus.

I have been trying to configure the IP block for PCIe on my Stratix V GX FPGA and I was following along the steps in this document https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-01097-1.3.pdf on page 2-3 which goes through the process of configuring the Hard IP through the MegaWizard Manager. I have followed all the steps in the process but whenever I try and compile the design in Quartus, I get the error: Error (11802): Can't fit design in device. Modify your design to reduce resources, or choose a larger device. I don't know why the design is not fitting on the Stratix FPGA when the design used and the process is all design specifically for Stratix V GX FPGA boards.