Honored ContributorI have CycloneIII on the board. Some synchronios signals come through the board to CycloneIII with phase shifts. Can these shifts be compensated in QuartusII for CycloneIII?
Honored ContributorIf you've properly entered timing constraints, and instructed the fitter to optimize hold timing, the fitter ought to be able to add delay to compensate for the phase shift. You'll need to specify the input delay for each individual signal. I assume these are regular I/O signals.
There are of course other methods. You could create a PLL with multiple outputs at different phases for sampling your input signals. You would then have to resynchronize these to a common clock domain. JakeHonored ContributorOk. It works. Thanks. The only strange thing is why Altera not remomeds to "combine individual or global tSU, tH, tPD, tCO, minimum tCO, or minimum tPD assignments with Input Delay or Output Delay assignments".
