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Altera_Forum's avatar
Altera_Forum
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16 years ago

How to check signal waveform.

I have this VHDL code within my architecture: architecture first of butterfly8 is signal butterfly8_r_Z1, butterfly8_r_Z2, butterfly8_r_Z3, butterfly8_r_Z4: std_logic_vector(31 downto 0); ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

i don't think you need to fit the design (where you are running into pin problems) to do a functional simulation.

just run Analysis and Synthesis (or even just Analysis and Elaboration), then Generate Functional Simulation Netlist, then Start Simulation.