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Altera_Forum
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16 years ago

How to check signal waveform.

I have this VHDL code within my architecture: architecture first of butterfly8 is signal butterfly8_r_Z1, butterfly8_r_Z2, butterfly8_r_Z3, butterfly8_r_Z4: std_logic_vector(31 downto 0); ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

There is usually more to a message than that. Can you expand it to get more info? What are the lines right around it? (For example, if it can't place the I/O it gives a message if it's a pure count, i.e. 700 pins needed, 650 available, or if it can't fit them all into I/O because of I/O standards, it lists some of the permutations it has tried).