How to check if a VERILOG_MACRO is defined in Quartus TCL script

I have a design that uses one of two clocks (CLK_A & CLK_B), selected based on an `ifdef check. The clock select macro is defined from the qsf file:

set_global_assignment -name verilog_macro "use_clk_a=1"

I have an sdc file that creates a clock 'dgn_clk' from the correct clock used in the design:

create_clock -name {dgn_clk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {CLK_A}]

Is there a way to select the right clock input port in TCL and assign it to dgn_clk based on checking if the corresponding Verilog macro is defined or not ?

Thanks.