Forum Discussion
Hello Vicky, Hello Abraham, Hello Tricky,
Thanks for your reactions: Your proposals are correct workarounds. However, every time this ALT_LOG is generated, manual correction will be necessary, so I share Abraham's conclusion.
As of Vicky's request/remark: I my initial request/detailed analysis referes to the fact that the "sclr" port was in some component definitions & some others it was not (be it all Altera lib or Altera IP code). That even within 1 lib directory, there are differences between component declarations & implementations. So I thought rechecking was not necessary, hence the misunderstanding.
But my inital queston remains still on the table: (I cannot help it :)): To do what is described in (be it an alternative solution for the issue or not) :
To perform functional and timing simulations, you must use the altera_mf.v library located in the <Quartus II installation directory>\eda\sim_lib directory. For VHDL, you must use the altera_mf.vhd library located in the <Quartus II installation directory>\eda\sim_lib directory. The VHDL component declaration file is located in the altera_mf_components.vhd library in the <Quartus II installation directory>\eda\sim_lib directory.
How do you do this ?
I select the altera_mf.vhd in Modelsim after launching it via Quartus. I click right, then I select "Edit Library Mapping", then "Browse", then I select a directory "C:/intelFpga_lite/17.1/quartus/eda/sim_lib."
The result is: altera_mf (unavailable) in the Library window?
So indeed I have a workaround, but I still wonder how does one do what is specified in the Intel/Altera web page?
Do you need to change the complete list of lib references or only reference?
Best regards,
Johi.