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Altera_Forum
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18 years ago

How to avoid negative slack?

Hi, Currently i'm developing an SOPC also with some self developed components. I'm using QII-6.1 and the CyclonII-Nios-Eval board. Clock frequency is 85MHz. Looked fine so far, but during add...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi,

I 'm using ALTERA fpga CYCLONE VI E. and working on Quartus 10.0 tool. when Enable the DMA in SOPC, after compilation Quartus showing worst case negative slack in "Time Quest Timing Analyzer" between DMA address BUS and Processor address BUS. How can i overcome this problem please suggest.

Please find the attachment regarding this.

Regards,

Jayachandra.