--- Quote Start ---
In this case adding a multicycle assignment in the right place could help.
--- Quote End ---
Use a multicycle assignment only if you know it is valid for the design.
In FPGAs, multicycle assignments are typically used for a case like a divide-by-n clock enable where you can use a multicycle setup of n to give the destination register a window of n clock cycles to latch in new data.
There are some cases in FPGAs where you can use a multicycle setup to delay which clock edge at the destination register latches the new data, but you also must use a multicycle hold to check that the old data remains at the destination register input until that last clock period.
Randall asked whether the timing violation is for a path going between clock domains. The multicycle situation in my previous paragraph used to come up sometimes for paths that go between two PLL clock domains. There is a better solution now that eliminates some of those cross-domain violations. Turn on "Enable Clock Latency" in the "More timing Settings" dialog box.
Honored Contributor
