How to avoid negative slack?

The handbook is the best place to camp. As a quick note to check some timing assumptions - check the from and to clock to make sure this timing failure is in one clock domain. If those two clocks are different, then the way to get rid of that timing error is completely different. You can put in the appropriate clock domain crossing logic, or relax the timing constraints depending on how the design works.

The number of loads pulling down the time could come from the source signal, not the clock source. Take a look in Quartus help at maximum fanout, maxfan. There are settings you can change to start effecting this, such as optimization for speed. Assignments -> settings -> analysis & synthesis -> optimization technique -> speed.