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Altera_Forum
Honored Contributor
Honored ContributorHow to avoid delay
Hello everyone, My problem is that i have an output available at a current clock cycle and i need to be read at the same clock cycle by another register. My top level entity is where i i...
Altera_ForumHonored Contributor
Honored ContributorYes i did try to omit the process and do the caclculation but the result got worsened. About register the output , in fact the output of the first module is the input of the second one and the output of the second module is the input of the first one. And it must be like that unfortunately..
