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Honored Contributor
Honored ContributorHow to avoid delay
Hello everyone, My problem is that i have an output available at a current clock cycle and i need to be read at the same clock cycle by another register. My top level entity is where i i...
Altera_ForumHonored Contributor
Honored ContributorHere is a screenshot for the waveform of my top level entity
In the second clock cycle q_labelling ( corresponding to the current_Label signal of the above code ) must take the qd (west in the code) of the same clock cycle but instead it takes the previous value.
