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This sounds exactly like a little experiment we ran.
I managed to create a 128 bit down counter that gave an FMax of 450 Mhz in Timequest (using a stratix 4, all pins virtual). To make it an upcounter you can simply invert the output.
It is split into 16x 8 bit down counters. Each counter outputs an "is_0" signal that is generated when counter = 1 and it is enabled. The enable of the next counter simply ANDs all the 0s together.
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I assume by parts you mean cascading counters. For example we can have a counter 0 ~ 999 either directly as one counter or cascaded into three 0~9 counters:
if(rising_edge(clk))then
if count1 /= 9
count1 <= count1 + 1;
else
count1 <= (others => '0');
if count2 /= 9 then
count2 <= count2 + 1;
else
count2 <= (others => '0');
if count3 /= 9 then
count3 <= count3 + 1;
else
count3 <= (others => '0');
end if;
end if;
end if;
end if;
in the case of single counter 0~999 it is enabled every clock.
In the case of three counters only count1 need update every clock but count2 every 10 clocks and count3 every 100 clocks so I assume these two counters can be multicycled 10 or 100
However to read final count value the phase of reading must be looked after carefully to account for multicycle delay.
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