Forum Discussion
sli30
New Contributor
7 years agoDear HRZ,
In the report, it includes I/O power, transceiver power, static and dynamic power. The I/O power and transceiver power are all around ~6 W, static power is ~6 W, dynamic power is ~9 W. In my understanding, the I/O power is caused by the data transfer between FPGA and DDR3 (DDR3 is the memory on Arria 10). How to understand transceiver power? I don't know what does it exactly mean and what reason caused it. In my OpenCL code, I defined input and output such as (__global int * input_a, __global int * input_b, __global int *output_c).
Thank you so much for your help.