Honored ContributorIn my design, sometimes I need to adjust bus width such as:
wire [10:0] a; wire [5:0] b; assign b={a[10:9],a[3:0]}; I always program like this. But it seems in some design it will cause problem and there are some errors which I can't understand appear in ModelSim simulation. I just wonder is there any other approaches to do bus width adjust which is better? Thanks very much.
Honored ContributorThe syntax is correct. I used it in ModelSim, too, but I never had problems.
What do you mean with "some errors"? Compile or functional simulation?Honored ContributorSorry Cris, actually I did not express exact. I just wonder whether this syntax may cause problem in static timing analysis? Based on my understanding, it should not since this is just connecting wire.
Honored ContributorWith functional simulation I indeed meant static timing analysis.
So the answer is still Yes: your syntax is correct. You probably have an error somewhere else.Honored ContributorThanks very much, I will check.
