Contributor
Regular ContributorHi,
Sorry for any confusion. For your information, as I look into the qsys_system.vhd (which I believe is the top level of Qsys HDL file) inside folder qsys_system\synthesis\, I am able to find the generics for qsys_component as following. Would you mind to further elaborate on the specific generic that you are looking for if it is something different from the existing?
"
component qsys_component is
generic (
counter_max : integer := 15;
write_address : std_logic_vector(31 downto 0) := "00000000000000000000000000000000"
);
port (
clk : in std_logic := 'X'; -- clk
reset_n : in std_logic := 'X'; -- reset_n
avm_write : out std_logic; -- write
avm_write_data : out std_logic_vector(31 downto 0); -- writedata
avm_write_address : out std_logic_vector(7 downto 0); -- address
avm_wait_request : in std_logic := 'X' -- waitrequest
);
end component qsys_component
"
Please let me know if there is any concern. Thank you.
Chee Pin
Contributor
