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Altera_Forum's avatar
Altera_Forum
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15 years ago

How to add 'enable' to combinational logic

I need a module to calculate the following:

d=((a xor b) xor c)

Each variable is 32 bits in size.

Also along with this I need signals like valid_in, valid_out and enable(en) for the module. Will the following constructs be useful for this module:

wire [31:0] out1, out2;

xor u1(out1,a,b);

xor u2(out2,out1,c);

assign d=out2;

always @(out2)

valid_out=1;

I can't figure out how to include the enable signal in the module. Can anyone suggest how to do that?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    always @(out2)
valid_out=1;

    This way, valid_out will stuck to one, because always @() is ignored in synthesis of combinational logic.

    You should think about the exact purpose of valid_in, valid_out and enable with the present example. It's not obvious. You can sketch a table that shows the intended states of these signals. I guess, the said signals can't be but dummies in this case. So valid_out = valid_in is probably all you should do.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I think, it would be easier to incorporate these signals if the design was sequential instead of combinational. It would also make it easier for me to calculate the latency of the module.

    Converting the design to sequential, I'm using a 2 bit shift register 'tmp' to calculate the 'valid_out' signal which goes high on the next clock cycle after the 'valid_in' signal.

    What do you think about this code?

    module xorcomp(

    input clk,

    input [31:0] a,

    input [31:0] b,

    input [31:0] c,

    input valid_in,

    output valid_out

    );

    reg [31:0] a_reg;

    reg [31:0] b_reg;

    reg [1:0] tmp; //the 2 bit shift register

    wire [31:0] a_wire; /*wires to copy the latched values of a, b, and c from registers a_reg, b_reg, c_reg*/

    wire [31:0] b_wire;

    wire [31:0] c_wire;

    always @(posedge clk)

    begin

    if(valid_in=='1')

    begin

    a_reg<=a;

    b_reg<=b;

    c_reg<=c;

    tmp<=2'b01;

    end

    else

    tmp<=tmp<<1;

    end

    assign valid_out=tmp[1];

    assign a_wire=a_reg;

    assign b_wire=b_reg;

    assign c_wire=c_reg;

    xor u1(out1,a_wire,b_wire);

    xor u2(out2,out1,c_wire);

    assign d=out2;

    endmodule