How to add 'enable' to combinational logic

I think, it would be easier to incorporate these signals if the design was sequential instead of combinational. It would also make it easier for me to calculate the latency of the module.

Converting the design to sequential, I'm using a 2 bit shift register 'tmp' to calculate the 'valid_out' signal which goes high on the next clock cycle after the 'valid_in' signal.

What do you think about this code?

module xorcomp(

input clk,

input [31:0] a,

input [31:0] b,

input [31:0] c,

input valid_in,

output valid_out

);

reg [31:0] a_reg;

reg [31:0] b_reg;

reg [1:0] tmp; //the 2 bit shift register

wire [31:0] a_wire; /*wires to copy the latched values of a, b, and c from registers a_reg, b_reg, c_reg*/

wire [31:0] b_wire;

wire [31:0] c_wire;

always @(posedge clk)

begin

if(valid_in=='1')

begin

a_reg<=a;

b_reg<=b;

c_reg<=c;

tmp<=2'b01;

end

else

tmp<=tmp<<1;

end

assign valid_out=tmp[1];

assign a_wire=a_reg;

assign b_wire=b_reg;

assign c_wire=c_reg;

xor u1(out1,a_wire,b_wire);

xor u2(out2,out1,c_wire);

assign d=out2;

endmodule