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Altera_Forum's avatar
Altera_Forum
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16 years ago

How to add constraint to Pll clk output

There are two clock sources whcih both generate from PLL in my design, inclk0 is 60MHz from input Pin, c0 is 100MHz and c1 is 160MHz. I only add a constraint to input clock(FMAX_REQUIREMENT "60 MHz")...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

As i mentioned before, the registers in IP are written in 100MHz clock, some of them are used in 160MHz, so the report shows timing violation but actually they won't lead system error. The timing violations are also exist in 50MHz and 80MHz design. Anyway, I will read all violation messages one by one.