How to add constraint to Pll clk output

A clock constraint can only clarify an existing timing requirement to the timing analyzer. The fact, that a timing violation is reported for your design along with an actual design failure suggests that the timing analyzer is aware of the timing requirements, but timing closure can't be achieved. In this case, an additional timing constraint doesn't change anything. The best method is to change the critical pathes, e.g by adding pipeline registers.

Timing constraints are typically necessary for external signals, or to inform the timing analyzer, that the default assumptions are not valid for particular signals.

I understand from your post, that you are facing many timing violations with the fast clock settings. You may want to trace the top red lines from the report to understand, what's the basic problem.