Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

How to add constraint to Pll clk output

There are two clock sources whcih both generate from PLL in my design, inclk0 is 60MHz from input Pin, c0 is 100MHz and c1 is 160MHz. I only add a constraint to input clock(FMAX_REQUIREMENT "60 MHz")...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I agree with this, now i want to find which pathes are critical to the error, but from timing analyzer report i can't find it and i analyze every violate signal. How can i add constraints to avoid the error or have any idea to locate the path?

Thank you very much!