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Altera_Forum's avatar
Altera_Forum
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16 years ago

How to add constraint to Pll clk output

There are two clock sources whcih both generate from PLL in my design, inclk0 is 60MHz from input Pin, c0 is 100MHz and c1 is 160MHz. I only add a constraint to input clock(FMAX_REQUIREMENT "60 MHz")...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The bit error only occurs at 100MHz and 160MHz condition, if i change the configuration to 50MHz and 80MHz or delete some modules in design, the system is OK, so i don't think it is the problem in design.

BTW, i use Stratix2 EP2S130F1020C5, the occupied resource is 20% Logic, 12% Register, 39% M512, 84% M4K, 33% MRAM and 19% DSP9x9. If i reduce the resource to 10% Logic, 10% Register, 39% M512, 10% M4K, 33% MRAM and 19% DSP9x9, system is OK.