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Altera_Forum
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16 years ago

How to add constraint to Pll clk output

There are two clock sources whcih both generate from PLL in my design, inclk0 is 60MHz from input Pin, c0 is 100MHz and c1 is 160MHz. I only add a constraint to input clock(FMAX_REQUIREMENT "60 MHz")...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Simply assume, that the timing analyzer gets sufficient information about the PLL clocks from the PLL parameters (you can check this in the timing analyzer report). The problem is in the design itself, not the clock. You have to check the timing analyzer report in detail to understand the nature of the timing violation, e.g. if it's caused by a signal crossing the clock domains or if it's within a clock domain.